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QuickLogic
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Part No. |
QL3012
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OCR Text |
...ilization and
inputs -- each driven by an input-only pin * Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enabl... |
Description |
qASIC 3 FPGA
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File Size |
158.78K /
16 Page |
View
it Online |
Download Datasheet |
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Intel
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Part No. |
A82596CA KU82596CA
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OCR Text |
...ng as read information, must be driven back to the 82596 over these pins to ensure that the correct parity check status is indicated by the 82596. pchk 127 o parity check. this pin is driven high one clock after rdy to inform read operation... |
Description |
High-performance 32-bit local area network coprocessor
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File Size |
739.58K /
76 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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